Dr. Vineet Jaiswal

Dr. Vineet Jaiswal is a dedicated academic and researcher in VLSI Design, Embedded Systems, and emerging nano-computing technologies. His work focuses on quantum architecture, nanomagnetic logic circuits, hardware modeling through Verilog, placement and routing algorithms, and machine-learning-assisted hardware design. With over 10 years of teaching and research experience, he serves as an Assistant Professor (Senior Scale) in the School of Computer Science, UPES Dehradun.

He completed his Ph.D. at National Institute of Technology Kurukshetra, where his research centered on developing advanced nanomagnetic logic architectures and optimizing design methodologies for next-generation computing systems. His expertise spans digital and embedded system design, quantum-inspired hardware, nanomagnetic QCA circuits, computational modeling, and ML-driven optimization techniques. Dr. Jaiswal has published several research papers in reputed journals and conferences and actively contributes to academic development through mentoring and scholarly service.

Dr. Jaiswal has over 10 years of academic experience, beginning as Teaching Personnel at Govind Ballabh Pant University of Agriculture and Technology. He later served as an Assistant Professor at Teerthanker Mahaveer University from 2014 to 2021, contributing significantly to teaching, research, and student project supervision. Since 2025, he has been working as Assistant Professor (Senior Scale) in the School of Computer Science, UPES Dehradun.

Quantum Architecture | Nanomagnetic Logic Circuits | Nano-Computing | Reversible Computing | Hardware Modeling using Verilog | Placement and Routing Algorithms | Machine Learning for VLSI Design | Neuromorphic Hardware | Intelligent Embedded Systems

Dr. Vineet Jaiswal's teaching philosophy is rooted in promoting strong conceptual clarity, practical insight, and continuous curiosity among engineering students. He believes meaningful learning occurs when theoretical foundations are closely linked with real-world applications, enabling students to think critically and solve problems creatively.

He is committed to creating an interactive, inclusive, and student-centered learning environment that encourages learners to question, explore, and innovate.

Elements of AI/ML | Design and Analysis of Algorithms | Digital Electronics | Electronic Devices and Circuits | Microprocessors and Microcontrollers | Computer Organization and Architecture | Foundational Subjects in Electronics and VLSI Design

Dr. Vineet Jaiswal has received several recognitions for his academic and research contributions. He has served as reviewer and session chair for reputed journals and conferences. His Ph.D. and M.Tech studies were supported through prestigious MHRD scholarships. He has also participated in more than 25 FDPs, workshops, STTPs, and seminars, reflecting his strong commitment to continuous academic growth.

Dr. Vineet Jaiswal has a strong record of scholarly engagement encompassing research publications, conference participation, academic service, and professional development. He has published several papers in reputed journals and conferences in the areas of quantum architecture, nanomagnetic logic circuits, VLSI design, and ML-assisted optimization techniques.

He has served as reviewer and session chair for respected journals and conferences, contributing to peer-review and academic quality enhancement. He has also mentored student research projects across VLSI, embedded systems, and quantum-inspired hardware design. His ongoing work continues to support advancements in VLSI, nano-computing, and emerging hardware architectures.

Email: vineet.jaiswal@ddn.upes.ac.in